Another BJT limitation is that both electrons and holes contribute to conduction. Presence of holes with their higher Holdoff Voltage V carrier lifetime causes the switching speed to be several orders of magnitude slower than for a power MOSFET of similar size and Bipolar voltage rating. Also, BJTs suffer from thermal runaway. Their Transistors forward voltage drop decreases with increasing temperature causing diversion of current to a single device when several MOS devices are paralleled.
They 0 are superior to the BJTs in high frequency applications where 1 10 switching power losses are important. Plus, they can withstand Maximum Current A simultaneous application of high current and voltage without Figure 2. Current-Voltage undergoing destructive failure due to second breakdown. MOSFETs can also be paralleled easily because the forward voltage drop increases with increasing temperature, ensuring an even distribution of current among all components.
This makes it more attractive to use the bipolar power transistor at the expense of worse high frequency performance. Over time, new materials, structures and processing techniques are expected to raise these limits. The parasitic JFET appearing between the two body implants restricts current flow when the depletion widths of the two adjacent body diodes extend into the drift region with increasing drain voltage.
The parasitic BJT can make the device susceptible to unwanted device turn-on and premature breakdown. The base resistance RB must be minimized through careful design of the doping and distance under the source region.
CGS is the capacitance due to the overlap of the source and the channel regions by the polysilicon gate and is independent of applied voltage. CGD consists of two parts, the first is the capacitance associated with the overlap of the polysilicon gate and the silicon underneath in the JFET region.
The second part is the capacitance associated with the depletion region immediately under the gate. CGD is a nonlinear function of voltage. Finally, CDS, the capacitance associated with the body-drift diode, varies inversely with the square root of the drain-source bias. The planar design has already been introduced in the schematic of Figure 3. The trench technology has the advantage of higher cell density but is more difficult to manufacture than the planar device.
For drain voltages below BVDSS and with no bias on the gate, no channel is D formed under the gate at a the surface and the drain voltage is entirely Source Source supported by the Gate reverse-biased body-drift p-n junction.
Two related Oxide phenomena can occur in Gate Oxide poorly designed and processed devices: punch-through and reach-through. This provides a current path between Drain source and drain and b causes a soft breakdown characteristics as shown Figure 5. There are tradeoffs to be made between RDS on that requires shorter channel lengths and punch-through avoidance that requires longer channel lengths.
The reach-through phenomenon occurs when the depletion region on the drift side of the body-drift p-n junction reaches the epilayer-substrate interface before avalanching takes place in the epi. These are normally negligible in high voltage devices but can 4 become significant in low voltage devices. Figure 9 shows the relative importance of each of the components to RDS on over the 5 3 voltage spectrum.
This 2 component is higher in high voltage devices due to the higher resistivity or 1 lower background carrier concentration in 0 0 5 10 15 the epi. At lower voltages, the RDS on is Drain Voltage Volts dominated by the channel resistance and the contributions from the metal to Figure 6.
The substrate contribution becomes more significant for lower breakdown voltage devices. This parameter is normally quoted for a Vgs that gives a drain current equal to about one half of the maximum current rating value and for a VDS that ensures operation in the constant current region. Transconductance is influenced by gate width, which increases in proportion to the active area as cell density increases. Cell density has increased over the years from around half a million per square inch in to around eight million for planar MOSFETs and around 12 million for the trench technology.
The limiting factor for even higher cell densities is the photolithography process control and resolution that allows contacts to be made to the source metallization in the center of the cells. Channel length also affects transconductance.
Reduced channel length is beneficial to both gfs and on-resistance, with punch-through as a tradeoff. The lower limit of this ID length is set by the ability to control the double-diffusion process and is around mm today.
Finally the lower the gate oxide thickness the higher gfs. Common values are Figure 7. Click here to sign up. Download Free PDF. Vrej Barkhordarian. A short summary of this paper. Download Download PDF. Translate PDF. Breakdown Voltage The metal oxide semiconductor field effect p-Substrate transistor MOSFET is based on the original field-effect Channel l transistor introduced in the 70s.
D The bipolar power transistor is SB a current controlled device. A Channel or Substrate large base drive current as G high as one-fifth of the collector current is required to S keep the device in the ON c state. Figure 1. Despite the very advanced state of manufacturability and lower costs of BJTs, these limitations have made the base drive circuit design more complicated and hence more expensive than the power MOSFET. Another BJT limitation is that both electrons and holes contribute to conduction.
Presence of holes with their higher Holdoff Voltage V carrier lifetime causes the switching speed to be several orders of magnitude slower than for a power MOSFET of similar size and Bipolar voltage rating. Also, BJTs suffer from thermal runaway. Their Transistors forward voltage drop decreases with increasing temperature causing diversion of current to a single device when several MOS devices are paralleled.
They 0 are superior to the BJTs in high frequency applications where 1 10 switching power losses are important. Plus, they can withstand Maximum Current A simultaneous application of high current and voltage without Figure 2. Current-Voltage undergoing destructive failure due to second breakdown. MOSFETs can also be paralleled easily because the forward voltage drop increases with increasing temperature, ensuring an even distribution of current among all components.
This makes it more attractive to use the bipolar power transistor at the expense of worse high frequency performance. Over time, new materials, structures and processing techniques are expected to raise these limits.
The parasitic JFET appearing between the two body implants restricts current flow when the depletion widths of the two adjacent body diodes extend into the drift region with increasing drain voltage. The parasitic BJT can make the device susceptible to unwanted device turn-on and premature breakdown. The base resistance RB must be minimized through careful design of the doping and distance under the source region.
CGS is the capacitance due to the overlap of the source and the channel regions by the polysilicon gate and is independent of applied voltage. CGD consists of two parts, the first is the capacitance associated with the overlap of the polysilicon gate and the silicon underneath in the JFET region.
The second part is the capacitance associated with the depletion region immediately under the gate. CGD is a nonlinear function of voltage. Finally, CDS, the capacitance associated with the body-drift diode, varies inversely with the square root of the drain-source bias. The planar design has already been introduced in the schematic of Figure 3.
The trench technology has the advantage of higher cell density but is more difficult to manufacture than the planar device.
For drain voltages below BVDSS and with no bias on the gate, no channel is D formed under the gate at a the surface and the drain voltage is entirely Source Source supported by the Gate reverse-biased body-drift p-n junction.
Two related Oxide phenomena can occur in Gate Oxide poorly designed and processed devices: punch-through and reach-through. This provides a current path between Drain source and drain and b causes a soft breakdown characteristics as shown Figure 5.
There are tradeoffs to be made between RDS on that requires shorter channel lengths and punch-through avoidance that requires longer channel lengths. The reach-through phenomenon occurs when the depletion region on the drift side of the body-drift p-n junction reaches the epilayer-substrate interface before avalanching takes place in the epi. These are normally negligible in high voltage devices but can 4 become significant in low voltage devices.
Figure 9 shows the relative importance of each of the components to RDS on over the 5 3 voltage spectrum.
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