We are just sharing the links that are already available on the internet. We recommend the candidate to buy this book. WhatsApp group Telegram group. Please send me this solution manual. Your email address will not be published. Flipkart: Sedra Smith book. Disclaimer: NO copyright infringement is intended here. July 21, We are just sharing the links that are already available on the internet.
We recommend the candidate to buy this book. WhatsApp group Telegram group. Please send me this solution manual. Your email address will not be published. Flipkart: Sedra Smith book. Disclaimer: NO copyright infringement is intended here. July 21, Kenneth C. EasyEngineering team try to Helping the students and others who cannot afford buying books is our aim.
For any quarries, Disclaimer are requested to kindly contact us , We assured you we will do our best. Questo documento in formato PDF 1. Give the four small-signal models Figs. Find the dc voltage at the collector, VC. Also, find the value of re. Replace the transistor with the T model of Fig. RC vsig vo v Rin Figure P7. The bias arrangement is not shown. Since a zero v BC implies operation in the active mode, the BJT can be replaced by one of the small-signal models of Figs.
Use the model of Fig. If a peak-to-peak output voltage of 1 V is measured at the collector, what are the peak-to-peak values of v be and ib? The bias circuitry is not shown. What is the dc voltage at the collector? Your circuit should show the values of all components, including the model parameters. What is the input resistance Rin? Disregarding how biasing is to be done, what is the largest possible voltage gain available for a signal source connected directly to the base and a very-high-resistance load?
What value of voltage gain results? The amplifier is to have the greatest possible voltage gain and the largest possible output signal but retain small-signal linear operation i.
If this circuit is to be equivalent to that in Fig. Find the overall voltage gain Gv. Also find the current gain, defined as the ratio of the load current to the current drawn from the signal source. Replace the transistor with the small-signal equivalent-circuit model of Fig.
Analyze the resulting amplifier equivalent circuit to show that D 7. Find appropriate values for RE and RC. What is the value of voltage gain realized from signal source to output?
This is different than Ro. In such a case, Rin depends on RL. To illustrate this point we show in Fig. It is Rf that makes the amplifier non-unilateral. Rout 7. Find Rin , Av o , and Ro. Now, if a 0. Also specify the bias current ID. Find Rin , Ro , and Av o. For this purpose, use the overall gain expression in Eq. What do you estimate the value of Rs to be? When Rs was shorted, but the circuit operation remained linear, the gain doubled. What must gm be?
Specify Re and the bias current IC. What is the input resistance of the amplifier? What is the overall voltage gain Gv? At what current IC should the transistor be biased for the input resistance Rin to equal that of the signal source? What is the resulting overall voltage gain? Find v o. RC isig vo Rsig Figure P7. If the maximum signal amplitude of the voltage between base and emitter is limited to 10 mV, what are the corresponding amplitudes of v sig and v o?
At this bias current, what are the maximum and minimum currents that the MOSFET will be conducting at the positive and negative peaks of the output sine wave? What must the peak amplitude of v sig be? If the peak amplitude of v be is to be limited to 5 mV, what is the lowest value of IE at which the BJT can be biased? At this bias current, what are the maximum and minimum currents that the BJT will be conducting at the positive and negative peaks of the output sine wave?
Thus determine the required amplitude of v sig. If the amplifier remained linear throughout this measurement, what must the values of gm and ro be? Arrange that the drain current is 1 mA, with about one-third of the supply voltage across each of RS and RD. Specify them to two significant digits.
For your design, how far is the drain voltage from the edge of saturation? Specify RS and RD to two significant digits. What is the value of VG created? If supplier specifications 2 allow kn to vary from 0. What value of RS should have been installed to limit the maximum value of ID to 1. What extreme values of current now result? What bias current results?
Use Eq. What must Vt be for this device? If a device for which Vt is 0. Design for a dc bias current of 0. Assume that the signal voltage on the source terminal of the FET is zero. Evaluate the sensitivity function, and give the expected variability of ID in this case. Specify all resistors to two significant digits. What is the corresponding range of IC? Comment on the efficacy of this bias design. Check your design by evaluating the resulting range of IE.
Comment on the efficacy of this biasing arrangement. For each of the following two transistors, find the voltages VD and VG. Find values for RE and RC so that a dc emitter current of 0. Use a current through RB2 equal to the base current. Also, what is the allowable signal swing at the collector? This can be achieved by connecting a resistor between base and emitter, as shown in Fig.
Figure P7. What is the dc voltage at the drain? What is the corresponding amplitude of the output voltage? What must the relationship of RE to R1 and R2 be? What is the lowest voltage that can be applied to the collector of Q3? What output voltage now results? Assume v sig to have a zero dc component.
What is the corresponding signal at the output? What is the new value of Gv? Neglect the Early effect. What is the output resistance of the source follower? Find the open-circuit voltage gain and the output resistance. Find the input resistance and the voltage gain. For simplicity, neglect the effect of ro. What must gm2 be?
If Q1 is biased at the same point as Q2 , what is the amplitude of the current pulses in the drain of Q1? What is the amplitude of the voltage pulses at the drain of Q1? What value of RD is required to provide 1-V pulses at the drain of Q2?
The signal vsig has a zero average. What must the dc voltage at the drain be? Calculate the dc drain current ID taking into account VA. Now, what value must the drain resistance RD have? We shall assume that VA is sufficiently large so that we can ignore the Early effect. The input signal vsig has a zero average. Calculate the dc drain current ID. What value must RD have?
This feedback amplifier and the gain expression should remind you of an op amp utilized in the inverting configuration. We shall study feedback formally in Chapter The power supply available is 15 V. Use an emitter current of approximately 2 mA and a current of about one-tenth of that in the voltage divider that feeds the base, with the dc voltage at the base about one-third of the supply.
It is required to design the circuit i. Calculate the dc bias current IC. This feedback amplifier circuit and the gain formula should remind you of an op amp connected in the noninverting configuration.
What base-to-collector open-circuit voltage gain does your design provide? Observe that the input resistance of the second stage, Rin2 , constitutes the load resistance of the first stage. Rin Figure P7. If the amplitude of the signal v be is to be limited to 5 mV, what is the largest signal at the input?
If the dc component of v sig is zero, find the dc emitter current. Compare the results with those obtained in b to find the advantages of bootstrapping. What will the new values of fL and AM be?
Also, find the dc voltages VB1 and VB2. Hint: Consider Q2 as an emitter follower fed by a voltage v b2 at its base. The folded-cascode configuration helps resolve this issue. Both the cascode and Wilson mirrors require at least 1 V or so for proper operation. Instructions to assist in setting up PSpice and Multism simulations for all the indicated problems can be found in the corresponding files on the website.
Section 8. Find R if Q1 and Q2 are matched with channel lengths of 0. What is the lowest possible value of VO? It is further required that the circuit operate for VO in the range of 0. Find the required value of R and the device dimensions. Note that while the circuit of Fig. The current source is required to operate for VO as high as 1. Neglect channel-length modulation. What is the minimum allowable value of VO for proper operation of the current source?
Specify the widths of all devices and the value of R. Find the output resistance of the current source Q2 and the output resistance of the current sink Q5. Show that the current transfer ratio is given by Eq. Assume that Q2 remains in the active mode, and neglect the Early effect. The Early voltage is 90 V. What is the maximum allowed value of VO while the current source continues to operate properly?
Repeat with two of the transistors diode connected and the third used to provide current output. For each possible input-diode combination, give the values of the output currents and of the VSG that results. Hint: Adapt Eq. Also, find the small-signal resistance of the diode-connected transistor Q2 in terms of gm2 , and hence the total resistance between the drain of Q1 and ground.
What is the voltage gain of the CS amplifier Q1? What is the total power dissipated in your circuit? Neglect ro for both devices. What are the new values of Av o and Ro? The transistor has a 0. Give the percentage difference between the actual and ideal value of IO. What is the lowest voltage at the output for which proper current-source operation is maintained?
If the deviation from unity is to be kept at 0. Replace each transistor with its T model and neglect r0. What must ID be? What value of gm is realized? Also, find the required device width W. Also, find W. It was fabricated in a 0. What are these values? Also, find the values of gm and ro. Then find the dc current in the feedback network and VDS. Verify that you were justified in neglecting the current in the feedback network when you found VGS.
Assume that the current-source load is ideal. What is the peak of the largest output sine-wave signal that is possible while the NMOS transistor remains in saturation? What is the corresponding input signal? Recall that Q2 and Q3 are matched. If v I consists of a dc bias component on which is superimposed a sinusoidal signal, find the value of the dc component that will result in the maximum possible signal swing at the output with almost-linear operation. What is the amplitude of the output sinusoid resulting?
Note: In practice, the amplifier would have a feedback circuit that caused it to operate at a point near the middle of its linear region. What will the extent of the linear region at the output become? For simplicity, ignore the effect of VA. Note that the biasing arrangement for Q1 is not shown.
Can you see the effectiveness of the CG as a current buffer? The output voltage must be able to swing to within approximately 0. If the channel length is an integer multiple of the minimum 0. If it is required to raise the gain by a factor of 2, what channel length would be required, and by what factor does the total gate area of the circuit increase? Two equal resistances Rs are inserted in the source leads to increase the output resistance of the current source.
Assume that the voltage at the common-gate node is approximately constant. Rs Figure P8. Figure P8. Note that the bias arrangement is not shown. The output at the collector is represented by its Norton equivalent circuit. Find the value of the current gain k and the output resistance Rout. Note that k is the short-circuit current gain and should be evaluated using the T model of the transistor with the collector short-circuited to ground. Rin 0. If the collector voltage undergoes a change of 10 V while the BJT remains in the active mode, what is the corresponding change in collector current?
That is, when fed with a current signal, it passes kisig 4. Complete the entries of the table at the bottom of the page. In the table, Av denotes the gain obtained in a cascode amplifier such as that in Fig.
Hint: We will see in Chapter 10 that the amplifier bandwidth increases with gm. Use a 0. What is the value of the minimum permitted output voltage? What is the maximum possible factor by which the output resistance can be raised, and at what value of Re is it achieved? Find gm1 , the output resistance of the amplifier, Ron , the output resistance of the current source, Rop , the overall output resistance, Ro , and the voltage gain, Av. The circuit in Fig.
The current source is to have the widest possible signal swing at its output. What is the highest allowable voltage at the output?
What is the value of Ro? Here we have grounded the input terminal i. By what factor is v y smaller than v x? Specifically, we wish to compare the a Show that for this circuit VOV is double that of the original v circuit, gm is half that of the original circuit, and o is vi double that of the original circuit. What is the allowable voltage range at the output?
Assume gm ro 1. Hint: Use the current-divider rule at the drain of Q1. The 0. What is the value of Ro achieved? Assume, for simplicity, that all transistors have equal parameters gm and ro.
Knowledge of this signal distribution is very useful in designing the circuit so as to allow for the required signal swings. As well, we have explicitly shown the resistance ro of each of the four transistors. For simplicity, we are assuming that the four transistors have the same gm and ro. The amplifier is fed with a signal v i. What is the voltage gain of the common-source stage? VDD 8. What is the output resistance? Ro Figure P8. Note that the short-circuit transconductance is determined by short-circuiting vo to ground and finding the current that flows through the short circuit, Gm vi.
Find the voltage gain Av. Assume the current sources are ideal. For each circuit determine Rin , Ro , and Av o. Comment on your results. Refer to Fig. What output current results? What are the voltages at the gates of Q2 and Q3? What is the lowest voltage at the output for which current-source operation is possible?
What is the output resistance of the mirror? The current source is required to operate with the voltage at its output terminal as low as —2. Give both the absolute value and the percentage change.
Neglect the Early effect in this derivation and assume a signal ground at the output. Assume that all three transistors are identical and neglect the Early effect. Also, assume a signal ground at the output. What must the bias current be? Assume that the bias current source has an output resistance equal to ro.
What do you estimate IO now to be? Find Ro. Also find the overall voltage gain, both open-circuited and with load. What will Rin and Gv become? Neglect the Early effect in both devices. Neglect the base current in Q2 in determining the current in Q1. For this purpose you can neglect RG. Neglecting ro , find Gv. Calculate the overall voltage gain. Section 9. Find the range of v id needed to steer the bias current from one side of the pair to the other. At each end of this range, give the value of the voltage at the common-source terminal and the drain voltages.
If vid for full current switching is to be 0. Find VOV , gm , ro , and Ad. Note: This is the dc voltage at the drains. Select the value of VOV so that the value of v id that steers the current from one side of the pair to the other is 0. What must the bias current I of the differential pair be relative to the bias current ID of the CS amplifier? What is the ratio of the power dissipation of the two circuits? What is the input common-mode voltage range for your design?
Both amplifiers use the same values of RD and supply voltages and are designed to dissipate equal amounts of power in their equilibrium or quiescent state. As well, all the transistors use the same channel length. What must the width W of the differential-pair transistors be relative to the width of the CS transistor? Let Q1 and Q2 be matched, and Q3 and Q4 be matched.
0コメント